Embodiments of present invention relate to semiconductor manufacturing processes. More particularly, embodiments of the present invention provide improved methods to realize a high-k metal gate device structure.
In the next generation of integrated circuit manufacturing process, complementary metal oxide semiconductor (CMOS) devices are often implemented in a high-k metal gate device structure. An example of such process includes forming dummy gate structures on a first semiconductor substrate. The dummy gate structure includes a sacrificial gate layer and a sacrificial gate dielectric material layer. A silicon germanium (SiGe) layer is embedded in the semiconductor substrate on both sides of the dummy gate of the PMOS portion, and then a silicon carbon (SiC) layer is embedded on a semiconductor substrate on both sides of the dummy gate structure of the NMOS portion of the CMOS. Then, after spacers are formed, ion implantation is carried out to form source/drain regions in the PMOS and NMOS regions. Subsequently, the dummy gate structures are replaced by the high-k metal gate structure, which includes a high-k gate dielectric and a metal gate.